{"id":183,"date":"2010-07-26T11:04:36","date_gmt":"2010-07-26T18:04:36","guid":{"rendered":"https:\/\/formidableengineeringconsultants.com\/?p=183"},"modified":"2016-01-17T17:45:24","modified_gmt":"2016-01-18T01:45:24","slug":"the-fpga-revolution-is-just-around-the-corner-again","status":"publish","type":"post","link":"https:\/\/formidableengineeringconsultants.com\/?p=183","title":{"rendered":"The FPGA Revolution Is Just Around The Corner…Again"},"content":{"rendered":"

I have spent a fair amount of my formative years in and around the field programmable gate array<\/a> (FPGA) industry.\u00a0 I participated in the evolution of FPGAs from a convenient repository for glue logic and a pricey but useful prototyping platform to a convenient repository for lots of glue logic, an affordable but still a little pricey platform to improve time-to-market and\u00a0a useful system-on-a-chip<\/a> platform.\u00a0 There was much talk about FPGAs going mainstream, displacing all but a few ASICs and becoming the vehicle of choice for most system implementations.\u00a0 It turns out that last step…the mainstreaming, the death of ASICs, the proliferating system-on-chip…is still underway.\u00a0 And maybe it’s just around the corner, again.\u00a0 But maybe it’s not.<\/p>\n

FPGA companies (well, Xilinx<\/a> and Altera<\/a>) appear to be falling prey to the classic disruptive technology<\/a> trap described by Clayton Christensen<\/a>.\u00a0 Listening to the calls of the deans of Wall Street and pursuing fat margins.\u00a0 Whether it’s Virtex<\/a> or Stratix<\/a>, both Xilinx and Altera are innovating at the high end delivering very profitable and very expensive parts that their biggest customers want and pretty much ignoring the little guys who are looking for cheap, functional and mostly\u00a0low power devices.<\/p>\n

This opens the door for players like Silicon Blue, Actel<\/a>\u00a0or Lattice<\/a> to pick a niche and exploit the heck out of it.\u00a0 Be it low power, non-volatile storage or\u00a0security, these folks are picking up some significant business here and there.\u00a0<\/p>\n

This innovation trap, however, ignores a huge opportunity that really only\u00a0a big player can address.\u00a0 I think that the biggest competitor to FPGAs is not ASSPs or ASICs or even other cheaper FPGAs.\u00a0 I think that what everyone needs to be watching out for is CPUs<\/a> and GPUs<\/a>.\u00a0<\/p>\n

Let’s face it, even with an integrated processor in your FPGA, you still really need to be a VHDL<\/a> or Verilog HDL<\/a> developer to build systems based on the FPGA.\u00a0 And how many HDL designers are there worldwide?\u00a0 Tens of thousands?\u00a0 Perhaps.\u00a0 Charitably.\u00a0 This illuminates another issue with systems-on-a-chip – software and software infrastructure. I think this might even be the most important issue acting as an obstacle to the wide adoption of programmable logic technology. To design a CPU or GPU-based system, you need to know C or C++.\u00a0 How many C developers are there worldwide?\u00a0 Millions?\u00a0 Maybe more.<\/p>\n

With a GPU you are entering the world of tesselation automata or systolic arrays.\u00a0 It is easier (but still challenging) to map a C program to a processor grid than sea of gates.\u00a0 And you also get to leverage the existing broad set of software debug and development tools.\u00a0 What would you prefer\u00a0to use\u00a0to develop your next system on a chip\u00a0– SystemC<\/a> with spotty support infrastructure or standard C<\/a> with deep and broad support infrastructure?<\/p>\n

The road to the FPGA revolution is littered with companies who’s products started as FPGA-based with a processor to help, but then migrated to a full multi-core CPU solution dumping the FPGA (except for data path and logic consolidation).\u00a0 Why is that?\u00a0 Because to make a FPGA solution work you need to be an expert immersed in FPGA architectures and you need to develop your own tools\u00a0to carefully divide hardware and software tasks.\u00a0 And in the end, to\u00a0get really great speeds and results, you need to keep tweaking your system and reassigning hardware and software tasks.\u00a0 \u00a0And then there’s the debugging challenge.\u00a0 In the end – it’s just hard.<\/p>\n

On\u00a0the other hand, grab an off-the-shelf multi-core processor, whack together some C code, compile it and run it and you get pretty good speeds and the same results.\u00a0 On top of that – debugging is better supported.<\/p>\n

I think FPGAs are great and someday they may be able to provide a real system-on-a-chip solution but they won’t until\u00a0FPGA companies stop thinking like semiconductor manufacturers and start thinking (and acting) like the software application solution providers they need to become.<\/p>\n","protected":false},"excerpt":{"rendered":"

I have spent a fair amount of my formative years in and around the field programmable gate array (FPGA) industry.\u00a0 I participated in the evolution of FPGAs from a convenient repository for glue logic and a pricey but useful prototyping platform to a convenient repository for lots of glue logic, an affordable but still a […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"om_disable_all_campaigns":false,"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[19,41,15,42],"tags":[43,90,44,27,92,38,89],"class_list":["post-183","post","type-post","status-publish","format-standard","hentry","category-design-automation","category-programmable-logic","category-software","category-systems-on-a-chip","tag-cpu","tag-design-automation","tag-gpu","tag-hardware","tag-programmable-logic","tag-revolutionary","tag-software"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t