{"id":490,"date":"2013-05-28T10:37:08","date_gmt":"2013-05-28T18:37:08","guid":{"rendered":"https:\/\/formidableengineeringconsultants.com\/?p=490"},"modified":"2013-12-09T09:46:39","modified_gmt":"2013-12-09T17:46:39","slug":"its-old-its-new-its-too-complicated-its-much-improved","status":"publish","type":"post","link":"https:\/\/formidableengineeringconsultants.com\/?p=490","title":{"rendered":"It&#8217;s Old&#8230;It&#8217;s New&#8230;It&#8217;s Too Complicated&#8230;It&#8217;s Much Improved&#8230;"},"content":{"rendered":"<p><a href=\"https:\/\/formidableengineeringconsultants.com\/wp-content\/uploads\/2013\/05\/IEEE-1149-1-jtag-picture.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-652 alignleft\" alt=\"IEEE-1149-1-jtag-picture\" src=\"https:\/\/formidableengineeringconsultants.com\/wp-content\/uploads\/2013\/05\/IEEE-1149-1-jtag-picture-300x252.png\" width=\"300\" height=\"252\" srcset=\"https:\/\/formidableengineeringconsultants.com\/wp-content\/uploads\/2013\/05\/IEEE-1149-1-jtag-picture-300x252.png 300w, https:\/\/formidableengineeringconsultants.com\/wp-content\/uploads\/2013\/05\/IEEE-1149-1-jtag-picture.png 830w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/a>That venerable electronic test standard <a href=\"http:\/\/standards.ieee.org\/findstds\/standard\/1149.1-2013.html\" target=\"_blank\">IEEE Std 1149.1<\/a> (also known as JTAG; also known as Boundary-Scan; also known as Dot 1) has just been freshened up.\u00a0 This is no ordinary freshening.\u00a0 The standard, last revisited in 2001, is long overdue for some clarification and enhancement.\u00a0 It&#8217;s been a long time coming and now&#8230;it&#8217;s here.\u00a0 While the guts remain the same and in good shape, some very interesting options and improvements have been added.\u00a0 The improvements are intended to provide support for testing and verification of the more complex devices currently available and to acknowledge the more sophisticated test algorithms and capabilities afforded by the latest hardware.\u00a0 There is an attempt, as well, (perhaps though, only as well as one can do this sort of thing) to anticipate future capabilities and requirements and to provide a framework within which such capabilities and requirements can be supported.\u00a0 Of course, since the bulk of the changes are optional their value will only be realized if the end-user community embraces them.<\/p>\n<p>There are only some minor clarifications or relaxations to the rules that are already established. For the most part, components currently compliant with the previous version of this standard will remain compliant with this one. There is but one &#8220;inside baseball&#8221; sort of exception.\u00a0 The long denigrated and deprecated BC_6 boundary-scan cell has finally been put to rest.\u00a0It is, with the 2013 version,\u00a0no longer supported or defined, so any component supplier who chose to utilize this boundary-scan cell &#8211; despite all warnings to contrary &#8211; must now provide their own BSDL package defining this BC_6 cell\u00a0if they upgrade to\u00a0using the STD_1149_1_2013 standard package for their BSDL definitions.<\/p>\n<p>While this is indeed\u00a0a major revision,\u00a0I must again emphasize that\u00a0all the new items introduced are optional.\u00a0 One of the largest changes\u00a0is in documentation capability incorporating\u00a0 the introduction of a new executable description language called <a href=\"http:\/\/grouper.ieee.org\/groups\/1149\/1\/1149P1-init.pdf\" target=\"_blank\">Procedural Description Language<\/a> (PDL)\u00a0to document test procedures unique to a component.\u00a0 PDL, a\u00a0<a href=\"http:\/\/en.wikipedia.org\/wiki\/Tcl\" target=\"_blank\">TCL<\/a>-like language,\u00a0was adopted from the work of the\u00a0<a href=\"http:\/\/grouper.ieee.org\/groups\/1687\/index.html\" target=\"_blank\">IEEE Std P1687 working group<\/a>. 1687 is a proposed IEEE Standard for the access to and operation of embedded instruments (1687 is therefore also known as iJTAG or Instrument JTAG). The first iteration of the standard was based on use of the 1149.1 Test Access Port and Controller to provide the chip access\u2014and a set of modified 1149.1-type Test Data Registers to create an access network for embedded instruments. PDL was developed to describe access to and operation of these embedded instruments.<\/p>\n<p>Now, let&#8217;s look at the details.\u00a0 The major changes are as follows:<\/p>\n<p>In the standard body:<\/p>\n<ul>\n<li>In order to allow devices to maintain their test logic in test mode,\u00a0a new, optional, test mode persistence controller\u00a0was introduced.\u00a0\u00a0This means that test logic (like the boundary-scan register) can remain behaviorally in test mode even if the active instruction does not force test mode. To support this, the TAP controller was cleaved into 2\u00a0parts.\u00a0 One part that\u00a0controls\u00a0test mode and the other that has all the rest of the TAP functionality. In support of this new controller, there are three new instructions: CLAMP_HOLD and TMP_STATUS (both of which access the new TMP status test data register) and CLAMP_RELEASE.<\/li>\n<li>In recognizing the\u00a0emerging requirement\u00a0for unique device identification codes\u00a0a new, optional ECIDCODE instruction was introduced\u00a0along with an associated\u00a0electronic chip identification test data register. \u00a0This instruction-register pair is intended to supplement the existing IDCODE and USERCODE instructions and allow for\u00a0access to\u00a0an Electronic Chip Identification value that could be used to identify and track individual integrated circuits.<\/li>\n<li>The problem of initializing a device for test has been addressed by providing a well-defined framework to use to formalize this process. The new, optional INIT_SETUP, INIT_SETUP_CLAMP, and INIT_RUN instructions\u00a0paired with their associated\u00a0initialization data and initialization status test data registers were provided to this end.\u00a0The intent is\u00a0that these instructions formalize the manner in which\u00a0programmable input\/output (I\/O)\u00a0can be set up prior to board or system testing, as well as any providing for the execution of any tasks required to put the system logic into a safe state for test.<\/li>\n<li>Recognizing that resetting a device can be complex and require many steps or phases,\u00a0a new, optional, IC_RESET instruction and its associated reset_select test data register\u00a0is defined\u00a0to provide formalized control of component reset functions through the TAP.<\/li>\n<li>Many devices now have a number of separate power domains that could result in sections of the device being powered down while other are powered up.\u00a0 A single, uniform boundary-scan register does not align well with that device style.\u00a0 So to support power domains that may be powered down but having a single test data register routed through these domains,\u00a0 an optional standard TAP to test data register interface is recommended that allows for segmentation of test data registers. The concept of register segments\u00a0allows for segments that may be excluded or included and is generalized sufficiently for utilization beyond the power domain example.<\/li>\n<li>There have also been a few enhancements to the boundary-scan register description to incorporate the following:<br \/>\n1. Optional excludable (but not selectable) boundary-scan register segments<br \/>\n2. Optional observe-only boundary-scan register cells to redundantly capture the signal value on all digital pins except the TAP pins<br \/>\n3. Optional observe-only boundary-scan register cells to capture a fault condition on all pins, including non-digital pins, except the TAP pins.<\/li>\n<\/ul>\n<p>The Boundary Scan Description Language annex was rewritten and includes:<\/p>\n<ul>\n<li>Increased clarity and consistency based on end-user feedback accumulated over the years.<\/li>\n<li>A technical change was made such that BSDL is no longer a \u201cproper subset\u201d of VHDL, but it is now merely \u201cbased on\u201d VHDL. This means that BSDL now maintains VHDL&#8217;s flavor but has for all intents and purposes been &#8220;forked&#8221;.<\/li>\n<li>As result of this forking, formal definitions of language elements are now included in\u00a0the\u00a0annex\u00a0instead of reliance on inheritance from VHDL.<\/li>\n<li>Also as a result of this forking, some changes to the BNF notation used, including definition of all the special character tokens, are in the annex.<\/li>\n<li>Pin mapping\u00a0now allows for documenting that a port is not connected to any device package pin in a specific mapped device package.<\/li>\n<li>The boundary-scan register description introduces new attributes for defining boundary-scan register segments, and introduces a requirement for documenting the behavior of an un-driven input.<\/li>\n<li>New capabilities are introduced for documenting the structural details of test data registers:<br \/>\n1.\u00a0Mnemonics may be defined that may be associated with register fields.<br \/>\n2. Name fields within a register or segment may be defined.<br \/>\n3. Types of cells used in a test data register (TDR) field may be defined.<br \/>\n4.\u00a0One may\u00a0hierarchically assemble segments into larger segments or whole registers.<br \/>\n5. Constraints may be defined on the values to be loaded in a register or register field.<br \/>\n6.\u00a0A register field or bit may be associated with specific ports<br \/>\n7. Power port may be associated with other ports.<\/li>\n<li>The User Defined Package has been expanded to support logic IP providers who may need to document test data register segments contained within their IP.<\/li>\n<\/ul>\n<p>As I stated earlier, a newly adopted\u00a0language, PDL, has been included in this version of the standard.\u00a0 The details of this language are included as part of Annex C. PDL is designed to\u00a0document the procedural and data requirements for some of the new instructions. PDL serves a descriptive purpose in that regard but, as such, it is also executable should a\u00a0system choose to interpret it.<\/p>\n<p>It was decided to\u00a0adopt and develop PDL to support the new capability of\u00a0\u00a0initializing internal test data register fields and configuring complex I\/Os prior to entering the EXTEST instruction.\u00a0 Since the data required for initialization could vary for each use of the component on each distinct board or system design there needed to be an algorithmic way to describe the data set-up and application., in order to configure the I\/O Since this version of the standard introduces new instructions for configuring complex I\/Os prior to entering the EXTEST instruction. As the data required for initialization could vary for each use of the component on each distinct board or system design, this created the need for a new language for setting internal test data register fields in order to configure the I\/O. It was decided to adopt PDL and tailor it to the BSDL register descriptions and the needs of IEEE 1149.1.<\/p>\n<p align=\"left\">Since the concept of BSDL and PDL working together is new and best explained via examples Annex D is provided to supply extended examples of BSDL and PDL used together to describe the structure and the procedures for use of new capabilities. Similarly Annex E provides\u00a0example pseudo-code for the execution of the PDL iApply command, the most complex of the new commands in PDL.<\/p>\n<p align=\"left\">So that is the new 1149.1 in a nutshell.\u00a0A fair amount of new capabilities. Some of it complex. All of it optional.\u00a0 Will you use it?<\/p>\n","protected":false},"excerpt":{"rendered":"<p>That venerable electronic test standard IEEE Std 1149.1 (also known as JTAG; also known as Boundary-Scan; also known as Dot 1) has just been freshened up.\u00a0 This is no ordinary freshening.\u00a0 The standard, last revisited in 2001, is long overdue for some clarification and enhancement.\u00a0 It&#8217;s been a long time coming and now&#8230;it&#8217;s here.\u00a0 While [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"om_disable_all_campaigns":false,"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"categories":[19,18,68,15,42,3],"tags":[28,90,27,29,71,58,26,23],"class_list":["post-490","post","type-post","status-publish","format-standard","hentry","category-design-automation","category-design-for-test","category-innovation","category-software","category-systems-on-a-chip","category-updates","tag-boundary-scan","tag-design-automation","tag-hardware","tag-ieee-std-1149-1","tag-ieee-std-1687","tag-risk","tag-test","tag-wheel"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/posts\/490","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=490"}],"version-history":[{"count":22,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/posts\/490\/revisions"}],"predecessor-version":[{"id":654,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=\/wp\/v2\/posts\/490\/revisions\/654"}],"wp:attachment":[{"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=490"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=490"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/formidableengineeringconsultants.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=490"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}